H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 159
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 159 of 1025
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6.1.4
Table 6.2 summarizes the registers of the bus controller.
Table 6.2
Notes: 1. Lower 16 bits of the address.
Name
Chip select 7
Upper column address strobe CAS
Lower column strobe
Wait
Bus request
Bus request acknowledge
Bus request output
Name
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus control register H
Bus control register L
Memory control register
DRAM control register
Refresh timer/counter
Refresh time constant register
2. Determined by the MCU operating mode.
Register Configuration
Bus Controller Registers
Symbol
CS7
LCAS
WAIT
BREQ
BACK
BREQO
ABWCR
ASTCR
WCRH
BCRH
RTCOR
Abbreviation
WCRL
BCRL
MCR
DRAMCR
RTCNT
I/O
Output
Output
Output
Input
Input
Output
Output
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Strobe signal indicating that area 7 is
selected.
2-CAS DRAM upper column address
strobe signal.
DRAM lower column address strobe signal.
Wait request signal when accessing
external 3-state access space.
Request signal that releases bus to
external device.
Acknowledge signal indicating that bus has
been released.
External bus request signal used when
internal bus master accesses external
space when external bus is released.
Rev. 3.00 Sep 15, 2006 page 125 of 988
Power-On
Reset
H'FF/H'00 *
H'FF
H'FF
H'FF
H'D0
H'3C
H'00
H'00
H'00
H'FF
Initial Value
2
Section 6 Bus Controller
Manual
Reset
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
REJ09B0330-0300
Address *
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
H'FED6
H'FED7
H'FED8
H'FED9
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