H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 531
H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
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Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the same value
as before is written.
Figure 10.51 shows the timing in this case.
Address
Write signal
Compare
match signal
TCNT
TGR
Figure 10.51 Contention between TGR Write and Compare Match
TGR write data
N
N
TGR write cycle
TGR address
T1
T2
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep 15, 2006 page 497 of 988
N+1
M
Inhibited
REJ09B0330-0300
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