H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 211
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
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6.6.2
When DRAM space is accessed in DMAC single address mode, full access (normal access) is
always performed. The DACK output goes low from the T
interface.
In modes other than DMAC single address mode, burst access can be used when accessing DRAM
space.
Figure 6.29 shows the DACK output timing for the DRAM interface when DDS = 0.
Figure 6.29 DACK
When DDS = 0
Read
Write
LCAS (LCAS)
DACK
DACK Output Timing when DDS = 0 (Example of DRAM Access)
CAS, (UCAS)
DACK
HWR, (WE)
HWR, (WE)
CSn (RAS)
D
D
A
15
15
23
DACK
to D
to D
to A
0
0
0
T
p
Row
T
r
Rev. 3.00 Sep 15, 2006 page 177 of 988
r
state in the case of the DRAM
T
c1
Column
T
Section 6 Bus Controller
c2
REJ09B0330-0300
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