H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 240
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 240 of 1025
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Section 7 DMA Controller (DMAC)
Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the
mode (sequential, idle, or repeat) in which transfer is to be performed.
For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode,
section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode.
Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR
to specify the data transfer direction (source or destination). The function of this bit is therefore
different in dual address mode and single address mode.
Rev. 3.00 Sep 15, 2006 page 206 of 988
REJ09B0330-0300
Bit 5
RPE
0
1
DMABCR
SAE
0
1
DMABCR
DTIE
0
1
0
1
Bit 4
DTDIR
0
1
0
1
Description
Transfer in sequential mode (no transfer end interrupt)
Transfer in sequential mode (with transfer end interrupt)
Transfer in repeat mode (no transfer end interrupt)
Transfer in idle mode (with transfer end interrupt)
Description
Transfer with MAR as source address and IOAR as destination
address
Transfer with IOAR as source address and MAR as destination address
Transfer with MAR as source address and DACK pin as write strobe
Transfer with DACK pin as read strobe and MAR as destination address
(Initial value)
(Initial value)
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