H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 639
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 639 of 1025
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Table 13.12 SCI Interrupt Sources
Note:
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance,
with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be
accepted in this case.
Channel
0
1
* This table shows the initial state immediately after a reset. Relative priorities among
Interrupt
Source
ERI
RXI
TXI
TEI
ERI
RXI
TXI
TEI
channels can be changed by means of the interrupt controller.
Description
Interrupt due to receive error
(ORER, FER, or PER)
Interrupt due to receive data full
state (RDRF)
Interrupt due to transmit data empty
state (TDRE)
Interrupt due to transmission end
(TEND)
Interrupt due to receive error
(ORER, FER, or PER)
Interrupt due to receive data full
state (RDRF)
Interrupt due to transmit data empty
state (TDRE)
Interrupt due to transmission end
(TEND)
Section 13 Serial Communication Interface (SCI)
Rev. 3.00 Sep 15, 2006 page 605 of 988
DTC
Activation
Not
possible
Possible
Possible
Not
possible
Not
possible
Possible
Possible
Not
possible
DMAC
Activation
Not
possible
Possible
Possible
Not
possible
Not
possible
Possible
Possible
Not
possible
REJ09B0330-0300
Priority *
High
Low
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