H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 503
H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
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Examples of Cascaded Operation
set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC
pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Figure 10.23 illustrates the operation when counting upon TCNT2 overflow/underflow has been
set for TCNT1, and phase counting mode has been designated for channel 2.
TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
Figure 10.22 illustrates the operation when counting upon TCNT2 overflow/underflow has been
TCNT1
clock
TCNT1
TCNT2
clock
TCNT2
TIOCA1,
TIOCA2
TGR1A
TGR2A
H'FFFF
H'03A1
Figure 10.22 Example of Cascaded Operation (1)
H'0000
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep 15, 2006 page 469 of 988
H'03A2
H'03A2
H'0000
REJ09B0330-0300
H'0001
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