H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 310

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
DREQ
DREQ
DREQ
DREQ Pin Falling Edge Activation Timing
Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7.31 shows an example of DREQ pin falling edge activated single address mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Rev. 3.00 Sep 15, 2006 page 276 of 988
REJ09B0330-0300
Figure 7.31 Example of DREQ
Address bus
DMA control
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of , and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle; DREQ pin high level sampling on the rising edge of
When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Idle
[1]
DREQ Pin Falling Edge Activated Single Address Mode Transfer
DREQ
DREQ
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
[5]
[6]
Single
DMA single
Request clear
Transfer source/
destination
Acceptance resumes
period
Idle
starts.
[7]
Bus release