H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 956
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
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Appendix B Internal I/O Register
TCR1—Timer Control Register 1
Rev. 3.00 Sep 15, 2006 page 922 of 988
REJ09B0330-0300
Bit
Initial value
Read/Write
:
:
:
—
—
7
0
CCLR1
R/W
Note: * Synchronous operating setting is performed by setting
6
0
Counter Clear
0
1
0
1
0
1
CCLR0
the SYNC bit in TSYR to 1.
R/W
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
5
0
CKEG1
R/W
4
0
Note: This setting is ignored when channel 1
Clock Edge
0
1
CKEG0
is in phase counting mode.
—
0
1
R/W
3
0
Note: This setting is ignored when channel 1 is in phase
Time Prescaler
Count at rising edge
Count at falling edge
Count at both edges
H'FFE0
0
1
0
1
0
1
TPSC2
counting mode.
R/W
2
0
0
1
0
1
0
1
0
1
Internal clock: counts on /1
Internal clock: counts on /4
Internal clock: counts on /16
Internal clock: counts on /64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
Internal clock: counts on ø/256
Counts on TCNT2 overflow/underflow
TPSC1
R/W
1
0
TPSC0
R/W
0
0
TPU1
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