H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 89
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 89 of 1025
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Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
2.7.2
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Specified
by @aa:8
Effective Address Calculation
Figure 2.13 Branch Address Specification in Memory Indirect Mode
(a) Normal Mode
Branch address
Specified
by @aa:8
Rev. 3.00 Sep 15, 2006 page 55 of 988
(b) Advanced Mode
Branch address
Reserved
REJ09B0330-0300
Section 2 CPU
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