H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 56
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 56 of 1025
- Download datasheet (6Mb)
Section 2 CPU
2.1.2
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
There are also differences in the address space, CCR and EXR functions, power-down state, etc.,
depending on the product.
Rev. 3.00 Sep 15, 2006 page 22 of 988
REJ09B0330-0300
High-speed operation
Two CPU operating modes
Power-down state
Register configuration
The MAC register is supported only by the H8S/2600 CPU.
Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
Number of execution states
The number of exection states of the MULXU and MULXS instructions.
Instruction
MULXU
MULXS
All frequently-used instructions execute in one or two states
Maximum clock rate
8/16/32-bit register-register add/subtract : 50 ns
8
16 ÷ 8-bit register-register divide
16
32 ÷ 16-bit register-register divide
Normal mode
Advanced mode
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Differences between H8S/2600 CPU and H8S/2000 CPU
8-bit register-register multiply
16-bit register-register multiply
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
: 20 MHz
: 600 ns
: 600 ns
: 1000 ns
: 1000 ns
H8S/2600
3
4
4
5
Internal Operation
H8S/2000
12
20
13
21
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