H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 706
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 706 of 1025
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Section 17 RAM
17.1.2
The on-chip RAM is controlled by SYSCR. Table 17.1 shows the address and initial value of
SYSCR.
Table 17.1 RAM Register
Note:
17.2
17.2.1
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Rev. 3.00 Sep 15, 2006 page 672 of 988
REJ09B0330-0300
Name
System control register
Bit 0
RAME
0
1
Bit
Initial value
R/W
* Lower 16 bits of the address.
Register Configuration
Register Descriptions
System Control Register (SYSCR)
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
:
R/W
—
7
0
—
—
6
0
SYSCR
Abbreviation
INTM1
R/W
5
0
INTM0
R/W
4
0
R/W
R/W
NMIEG
R/W
3
0
H'01
Initial Value
—
—
2
0
R/W
—
1
0
H'FF39
Address *
(Initial value)
RAME
R/W
0
1
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