H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 533

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 10.53 shows the timing in this case.
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Figure 10.53 Contention between TGR Read and Input Capture
X
TGR read cycle
T1
TGR address
M
T2
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep 15, 2006 page 499 of 988
M
REJ09B0330-0300

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