S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 107

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S9S12P32J0VFTR

Manufacturer Part Number
S9S12P32J0VFTR
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12P32J0VFTR

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
Chapter 3
Memory Map Control (S12PMMCV1)
3.1
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources.
3.1.1
Freescale Semiconductor
Local Addresses
Global Addresse
Aligned Bus Access
Misaligned Bus Access
NS
SS
Unimplemented Address Ranges
P-Flash
D-Plash
NVM
IFR
(Item No.)
Rev. No.
01.03
01.04
01.05
Introduction
(Submitted By)
Figure 3-1
Glossary
22.APR.2010
10.JAN.2008
13.JAN.2010
Term
Date
shows a block diagram of the S12PMMC module.
Figure 3-2
Sections
Affected
General
General
S12P-Family Reference Manual, Rev. 1.13
Address within the CPU12’s Local Address Map
Address within the Global Address Map
Bus access to an even address.
Bus access to an odd address.
Normal Single-Chip Mode
Special Single-Chip Mode
Address ranges which are not mapped to any on-chip ressource.
Program Flash
Data Flash
Non-volatile Memory; P-Flash or D-Flash
NVM Information Row. Refer to FTMRC Block Guide
Table 3-1. Revision History Table
Table 3-3. Glossary Of Terms
Table 3-2.
Removed references to the MMCCTL1 register
Added reserved registers
Substantial Change(s)
Definition
Minor Changes
(Figure
3-10)
(Figure
3-10)
107

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