S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 191

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

6.5.4
A trigger is generated immediately when one of up to 3 given events occurs
Scenario 3 is possible with S12SDBGV1 SCR encoding
6.5.5
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate
event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A
cause a trigger. This is possible by using CompA and CompC to match on the same address as shown.
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2
comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
Freescale Semiconductor
Scenario 3
Scenario 4
SCR3=0001
SCR3=1110
SCR1=0100
SCR1=0110
Figure 6-33. Scenario 4b (with 2 comparators)
SCR1=0000
State1
S12P-Family Reference Manual, Rev. 1.13
Figure 6-32. Scenario 4a
Figure 6-31. Scenario 3
M1
M2
State1
State1
State 3
State 3
M012
Final State
M2
M0
M0
M0
M1
M2
M1
M2
Final State
Final State
State2
State2
M0
M01
S12S Debug Module (S12SDBGV2)
SCR2=0011
SCR2=1100
M1 disabled in
range mode
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