S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 312

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S9S12P32J0VFTR

Manufacturer Part Number
S9S12P32J0VFTR
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12P32J0VFTR

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
Analog-to-Digital Converter (ADC12B10C)
312
ETRIGCH[3:0]
SMP_DIS
Field
3–0
4
1. Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
ETRIGSEL
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
ETRIGCH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
Table 9-3. ATDCTL1 Field Descriptions (continued)
Table 9-5. External Trigger Channel Select Coding
SRES1
0
0
1
1
ETRIGCH2
S12P-Family Reference Manual, Rev. 1.13
Table 9-4. A/D Resolution Coding
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
SRES0
0
1
0
1
ETRIGCH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
Description
ETRIGCH0
A/D Resolution
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10-bit data
12-bit data
Reserved
8-bit data
Table
9-5.
External trigger source is
ETRIG0
Reserved
Reserved
ETRIG1
ETRIG2
ETRIG3
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN9
AN9
AN9
AN9
AN9
AN9
Freescale Semiconductor
(1)
1
1
1

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