S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 229

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

7.3.2.19
The CPMUHTTR register configures the trimming of the S12CPMU temperature sense.
Read: Anytime
Write: Anytime
Freescale Semiconductor
0x02F7
HTTR[3:0]
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
Reset
HTOE
Field
details.
3–0
7
W
R
HTOE
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
High Temperature Trimming Register (CPMUHTTR)
High Temperature Trimming Bits — See
0
7
= Unimplemented or Reserved
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
0
0
6
Bit
S12P-Family Reference Manual, Rev. 1.13
Increases V
Increases V
Increases V
Increases V
0
0
5
HT
HT
HT
HT
twice of HTTR[2]
twice of HTTR[1]
twice of HTTR[0]
(to compensate Temperature Offset)
Table 1-27
0
0
4
Trimming Effect
Description
for trimming effects.
S12 Clock, Reset and Power Management Unit (S12CPMU)
HTTR3
F
3
HTTR2
F
2
HTTR1
F
1
HTTR0
F
0
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