S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 134

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S9S12P32J0VFTR

Manufacturer Part Number
S9S12P32J0VFTR
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12P32J0VFTR

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
Background Debug Module (S12SBDMV1)
clock please make sure that the communication rate is adapted accordingly and a communication time-out
(BDM soft reset) has occurred.
5.3
5.3.1
Table 5-1
5.3.2
A summary of the registers associated with the BDM is shown in
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
134
0x3_FF00
0x3_FF01
0x3_FF02
0x3_FF03
0x3_FF04
Address
Global
Memory Map and Register Definition
shows the BDM memory map when BDM is active.
Module Memory Map
Register Descriptions
Reserved
Reserved
Reserved
Reserved
BDMSTS
Register
Name
0x3_FF0C–0x3_FF0E
0x3_FF00–0x3_FF0B
0x3_FF10–0x3_FFFF
Global Address
0x3_FF0F
W
W
W
W
W
R
R
R
R
R
ENBDM
Bit 7
X
X
X
X
X
S12P-Family Reference Manual, Rev. 1.13
Figure 5-2. BDM Register Summary
= Unimplemented, Reserved
= Indeterminate
BDMACT
Table 5-1. BDM Memory Map
X
X
X
X
6
Family ID (part of BDM firmware ROM)
X
X
X
X
5
0
BDM firmware ROM
BDM firmware ROM
BDM registers
Module
SDV
4
X
X
X
X
Figure
TRACE
X
X
X
X
3
0
5-2. Registers are accessed by
= Implemented (do not alter)
= Always read zero
X
X
X
X
2
0
Freescale Semiconductor
(Bytes)
Size
UNSEC
240
12
3
1
X
X
X
1
0
Bit 0
X
X
X
0
0

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