S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 117

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

3.5
Each memory can be implemented in its maximum allowed size. But some devices have been defined for
smaller sizes, which means less implemented pages. All non implemented pages are called unimplemented
areas.
3.5.0.1
The global memory spaces reserved for the internal resources (RAM, D-Flash, and P-Flash) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the SoC Guide for further details.
and
spaces have fixed top addresses.
In single-chip modes accesses by the CPU12 (except for firmware commands) to any of the
unimplemented areas (see
to the unimplemented areas are allowed but the data will be undefined.
No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM
module (Refer to BDM Block Guide).
Freescale Semiconductor
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Table 3-8
1. RAMSIZE is the hexadecimal value of RAM SIZE in bytes
2. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes
Registers has a fixed size of 1KB, accessible via xbus0.
SRAM has a maximum size of 11KB, accessible via xbus0.
D-Flash has a fixed size of 4KB accessible via xbus0.
P-Flash has a maximum size of 224KB, accessible via xbus0.
NVM resources (IFR) including D-Flash have maximum size of 16KB (PPAGE 0x01).
Implemented Memory in the System Memory Architecture
Implemented Memory Map
Internal Resource
show the memory spaces occupied by the on-chip resources. Please note that the memory
System RAM
Registers
D-Flash
P-Flash
Figure
Table 3-8. Global Implemented Memory Space
3-11) will result in an illegal access reset (system reset). BDM accesses
S12P-Family Reference Manual, Rev. 1.13
0x4_0000 minus FLASHSIZE
0x0_4000 minus RAMSIZE
Bottom Address
RAM_LOW =
PF_LOW =
0x0_0000
0x0_4400
(1)
(2)
Memory Map Control (S12PMMCV1)
Top Address
0x3_FFFF
0x0_03FF
0x0_3FFF
0x0_53FF
Figure 3-11
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