S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 272

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
8.3.2.16
This register reflects the status of the MSCAN transmit error counter.
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
272
Module Base + 0x000E
Module Base + 0x000F
Write: Unimplemented
Write: Unimplemented
Reset:
Reset:
W
W
R
R
MSCAN Transmit Error Counter (CANTXERR)
RXERR7
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
0
0
7
7
Figure 8-19. MSCAN Transmit Error Counter (CANTXERR)
Figure 8-18. MSCAN Receive Error Counter (CANRXERR)
RXERR6
TXERR6
= Unimplemented
= Unimplemented
0
0
6
6
S12P-Family Reference Manual, Rev. 1.13
RXERR5
TXERR5
0
0
5
5
RXERR4
TXERR4
NOTE
NOTE
0
0
4
4
RXERR3
TXERR3
3
0
3
0
RXERR2
TXERR2
0
0
2
2
Access: User read/write
Access: User read/write
RXERR1
TXERR1
Freescale Semiconductor
0
0
1
1
RXERR0
TXERR0
0
0
0
0
(1)
(1)