S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 42

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

Device Overview MC9S12P-Family
1.7.4.6
This pin provides ground for the oscillator and the phased-locked loop. The voltage supply of nominally
1.8V is derived from the internal voltage regulator.
1.7.4.7
1.8
For the system clock description please refer to chapter
Management Unit
1.9
The MCU can operate in different modes. These are described in
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging.
42
System Clock Description
Modes of Operation
VSSPLL — Ground Pin for PLL
Power and Ground Connection Summary
(S12CPMU).
Mnemonic
VDDX[2:1]
VSSX[2:1]
VSSPLL
VDDR
VDDA
VSSA
VSS3
VRH
VRL
Table 1-9. Power and Ground Connection Summary
S12P-Family Reference Manual, Rev. 1.13
Nominal
Voltage
5.0 V
5.0 V
5.0 V
5.0 V
1.9.2 Low Power
0 V
0 V
0 V
0V
0V
External power supply to internal voltage
regulator
External power and ground, supply to pin
drivers
Operating voltage and ground for the
analog-to-digital converters and the
reference for the internal voltage regulator,
allows the supply voltage to the A/D to be
bypassed independently.
Reference voltages for the analog-to-digital
converter.
Internal power and ground generated by
internal regulator for the internal core.
Provides operating voltage and ground for
the phased-locked loop. This allows the
supply voltage to the PLL to be bypassed
independently. Internal power and ground
generated by internal regulator.
Chapter 7, “S12 Clock, Reset and Power
Operation.
Description
1.9.1 Chip Configuration
Freescale Semiconductor
Summary.