S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 261

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

8.3.2.4
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
1. Read: Anytime
Freescale Semiconductor
Module Base + 0x0003
TSEG2[2:0]
TSEG1[3:0]
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
SAMP
Field
6-4
3-0
7
Reset:
W
R
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
9.
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
10.
MSCAN Bus Timing Register 1 (CANBTR1)
SAMP
0
7
BRP5
0
0
0
0
1
:
TSEG22
Figure 8-7. MSCAN Bus Timing Register 1 (CANBTR1)
SJW1
BRP4
Table 8-6. Synchronization Jump Width (continued)
0
1
1
0
0
0
0
1
:
0
6
Table 8-8. CANBTR1 Register Field Descriptions
(1)
Figure
Figure
S12P-Family Reference Manual, Rev. 1.13
BRP3
.
0
0
0
0
1
:
TSEG21
Table 8-7. Baud Rate Prescaler
8-44). Time segment 2 (TSEG2) values are programmable as shown in
8-44). Time segment 1 (TSEG1) values are programmable as shown in
0
5
BRP2
0
0
0
0
1
:
TSEG20
SJW0
BRP1
0
4
1
0
1
0
0
1
1
1
:
Description
Freescale’s Scalable Controller Area Network (S12MSCANV3)
BRP0
TSEG13
0
1
0
1
1
:
3
0
Synchronization Jump Width
TSEG12
Prescaler value (P)
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
0
2
64
1
2
3
4
:
Access: User read/write
TSEG11
0
1
TSEG10
Table 8-
Table 8-
0
0
261
(1)