S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 234

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.21
This registers configures the external oscillator (OSCLCP).
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
234
0x02FA
OSCFILT
OSCBW
Reset
OSCE
Field
4-0
7
6
W
R
OSCE
Oscillator Enable Bit — This bit enables the external oscillator (OSCLCP). The UPOSC status bit in the
CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source
of the COP or RTI. A loss of oscillation will lead to a clock monitor reset.
0 External oscillator is disabled.
1 External oscillator is enabled.Clock monitor is enabled.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Oscillator Filter Bandwidth Bit — If the VCOCLK frequency exceeds 25 MHz wide bandwidth must be
selected.The Oscillator Filter is described in more detail at
0 Oscillator filter bandwidth is narrow (window for expected OSCCLK edge is one VCOCLK cycle).
1 Oscillator filter bandwidth is wide (window for expected OSCCLK edge is three VCOCLK cycles).
Oscillator Filter Bits — When using the oscillator a noise filter can be enabled, which filters noise from the
OSCCLK and detects if the OSCCLK is qualified or not (quality status shown by bit UPOSC).
The f
calculated integer value to enable the oscillator filter).
0x0000 Oscillator Filter disabled.
else Oscillator Filter enabled:
S12CPMU Oscillator Register (CPMUOSC)
0
7
REFCLK for PLL is IRCCLK.
REFCLK for PLL is the external oscillator clock divided by REFDIV.
Write to this register clears the LOCK and UPOSC status bits.
If the chosen VCOCLK-to-OSCCLK ratio divided by two is not an integer
number, then the filter can not be used and the OSCFILT[4:0] bits must be
set to 0.
VCO
Mode with OSCE bit is already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator t
-to- f
OSCBW
OSC
Figure 7-28. S12CPMU Oscillator Register (CPMUOSC)
0
6
ratio divided by two must be an integer value. The OSCFILT[4:0] bits must be set to the
Table 7-22. CPMUOSC Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
0
0
5
UPOSC
before entering Pseudo Stop Mode.
NOTE.
NOTE.
0
4
Description
Section 7.4.5.2, “The Adaptive Oscillator
0
3
OSCFILT[4:0]
0
2
Freescale Semiconductor
0
1
Filter.
0
0