S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 115

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S9S12P32J0VFTR

Manufacturer Part Number
S9S12P32J0VFTR
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12P32J0VFTR

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
Expansion of the BDM Local Address Map
PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global
address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
The four BDMPPR Program Page index bits allow access to the full 256KB address map that can be
accessed with 18 address bits.
The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and,
in the case the CPU is executing a firmware command which uses CPU instructions, or by a BDM
hardware commands. See the BDM Block Guide for further details. (see
Freescale Semiconductor
Bit17
Bit17
BDMPPR Register [3:0]
BDMPPR Register [3:0]
Figure 3-9. BDMPPR Address Mapping
S12P-Family Reference Manual, Rev. 1.13
Global Address [17:0]
Global Address [17:0]
BDM HARDWARE COMMAND
BDM FIRMWARE COMMAND
Bit14
Bit14
Bit13
Bit13
BDM Local Address [13:0]
CPU Local Address [13:0]
Figure
Memory Map Control (S12PMMCV1)
3-9).
Bit0
Bit0
115

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