S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 73

• Manufacturer Part Number: S9S12P32J0VFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 32K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P32J0VFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

1. Read: Anytime
2.3.18
Freescale Semiconductor
Address 0x0242
7-6, 3-1
Write: Anytime
DDRT
DDRT
DDRT
Field
Field
PTIT
Reset
7-0
4,0
5
W
R
Port T input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the API_EXTCLK forces the I/O state
to be an output if enabled. In these cases the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
DDRT7
Port T Data Direction Register (DDRT)
0
7
DDRT6
0
6
Figure 2-16. Port T Data Direction Register (DDRT)
Table 2-16. DDRT Register Field Descriptions
Table 2-15. PTIT Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
DDRT5
5
0
DDRT4
0
4
Description
Description
DDRT3
0
3
DDRT2
0
2
Port Integration Module (S12PPIMV1)
Access: User read/write
DDRT1
0
1
DDRT0
0
0
73
(1)