S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 437

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S9S12P32J0VFTR

Manufacturer Part Number
S9S12P32J0VFTR
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12P32J0VFTR

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
13.3.2.4
This Flash register is reserved for factory testing.
All bits in the FRSV0 register read 0 and are not writable.
13.3.2.5
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Freescale Semiconductor
CCOBIX[1:0]
Offset Module Base + 0x000C
Offset Module Base + 0x0004
Reset
Reset
Field
2–0
W
W
R
R
CCIE
Flash Reserved0 Register (FRSV0)
Flash Configuration Register (FCNFG)
0
0
0
Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register
array is being read or written to. See
for more details.
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 13-9. Flash Configuration Register (FCNFG)
Figure 13-8. Flash Reserved0 Register (FRSV0)
Table 13-11. FCCOBIX Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
0
0
0
0
5
5
Section 13.3.2.11, “Flash Common Command Object Register
IGNSF
0
0
0
4
4
Description
0
0
0
0
3
3
128 KByte Flash Module (S12FTMRC128K1V1)
0
0
0
0
2
2
FDFD
0
0
0
1
1
(FCCOB),”
FSFD
0
0
0
0
0
437

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