DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 104

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 10-7. Transmit Framer Pin Signal Timing Source Select
10.2.3.3 Receive Line Interface Pin Timing Source Selection
(RPOSn/RDATn, RNEGn/RLCVn/ROHMIn)
The receive line interface signal pin group must clocked in with the RLCLK clock input pin. When the LIU is
enabled, the receive line interface pins are not used so there is no valid clock reference.
Table 10-8. Receive Line Interface Pin Signal Timing Source Select
10.2.3.4 Receiver Framer and Fractional Pin Timing Source Selection
(RSERn, RSOFOn/RDENn/RFOHENOn, RFOHENIn/RPDENIn, RPDATn)
The receive framer and fractional signal pin group has the same functional timing clock source as the RCLKOn pin
described in
Other clock pins can be used for the external timing. The RCLKOn receive clock output pin is always a valid output
clock for external logic to use for these signals when PORT.CR3.RFTS=0.
The receive framer and fractional timing select bit (RFTS) is used to select input or output clock pin timing. When
RFTS=0, output clock timing is selected. When RFTS=1, input clock timing is selected. If RFTS is set for input
clock timing and an output clock pin is used, or If RFTS is set for output clock timing and an input clock pin is used,
then the setup, hold and delay timings, as specified in
of RFTS=1 and other modes in which there is no input clock pin available for external timing since the clock source
is derived internally from the RX LIU or the CLAD.
LOOPT
1
1
1
0
0
0
0
0
0
0
0
0
LOOPT
X
X
Table
not LLB, DLB or PLB (00X)
PLB (011) or DLB (100) or
PLB (011) or DLB (100)
10-5.
DLB&LLB (110)
not PLB (011)
not PLB (011)
ALB (001)
PLB (011)
PLB (011)
LLB (010)
LBM[2:0]
LBM[2:0]
XXX
XXX
XXX
XXX
XXX
LIUEN
LIUEN
0
1
X
X
X
X
X
X
0
1
0
1
0
1
Table
104
CLADC
18-1, will not be valid. There are some combinations
X
X
X
X
X
X
X
X
X
X
0
1
CLADC
X
X
TFTS
0
1
1
0
0
0
0
0
1
1
1
1
TCLKOn, TLCLKn, RCLKOn
RLCLKn
No valid timing to any input
clock pin
TCLKOn, TLCLKn, RCLKOn
TCLKOn, TLCLKn, RCLKOn
TCLKOn, RCLKOn
TCLKOn
TCLKOn, TLCLKn
No valid timing to any input
clock pin
TCLKIn
RLCLKn
No valid timing to any input
clock pin
RLCLKn
No valid timing to any clock pin
VALID TIMING TO THESE
VALID TIMING TO THESE
CLOCK PINS
CLOCK PINS