DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 329
DS3184DK
Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3184DK
Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Receive F1 Byte (RF1[7:0]) – These eight bits are the integrated version of the F1 byte as extracted
from the receive PLCP frame.
Bits 2 to 0: Receive Link Status Signal (LSS[2:0]) – These three bits are the integrated version of the receive
link status signal (G1[6:8]) as extracted from the receive PLCP frame.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Receive M2 Byte (RM2[7:0]) – These eight bits are the integrated version of the M2 byte as
extracted from the receive PLCP frame.
Bits 7 to 0: Receive M1 Byte (RM1[7:0]) – These eight bits are the integrated version of the M1 byte as extracted
from the receive PLCP frame.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Receive Z2 Byte (RZ2[7:0]) – These eight bits are the integrated version of the Z2 byte as extracted
from the receive PLCP frame.
Bits 7 to 0: Receive Z1 Byte (RZ1[7:0]) – These eight bits are the integrated version of the Z1 byte as extracted
from the receive PLCP frame.
RM27
RM17
RF17
RZ27
RZ17
15
15
15
—
0
7
0
0
7
0
0
7
0
RM26
RM16
RF16
RZ26
RZ16
14
14
14
—
0
6
0
0
6
0
0
6
0
PLCP.RFGBR
PLCP Receive F1 and G1 Byte Register
(1,3,5,7)76h
PLCP.RM12BR
PLCP Receive M1 and M2 Byte Register
(1,3,5,7)78h
PLCP.RZ12BR
PLCP Receive Z1 and Z2 Byte Register
(1,3,5,7)7Ah
RM25
RM15
RF15
RZ25
RZ15
13
13
13
—
0
5
0
0
5
0
0
5
0
RM24
RM14
RF14
RZ24
RZ14
12
—
12
12
0
0
0
0
0
0
4
4
4
329
RM23
RM13
RF13
RZ23
RZ13
11
11
11
—
0
3
0
0
3
0
0
3
0
RM22
RM12
RF12
LSS2
RZ22
RZ12
10
10
10
0
2
0
0
2
0
0
2
0
RM21
RM11
RF11
LSS1
RZ21
RZ11
9
0
1
0
9
0
1
0
9
0
1
0
RM20
RM10
RF10
LSS0
RZ20
RZ10
8
0
0
0
8
0
0
0
8
0
0
0
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