DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 321

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bit 1: Error Count Control (ECC) – When 0, framing errors, BIP-8 parity errors, and REI errors will not be counted
during an OOF condition (BIP-8 parity error counting will resume in the second full frame after an OOF condition is
cleared). When 1, framing errors, BIP-8 parity errors, and REI errors will be counted during an OOF condition.
Bit 0: Force Framer Re-synchronization (FRSYNC) – A 0 to 1 transition forces the framer into the “Search state.
Once the framer acquires lock, the data path frame counters will be updated regardless of whether an OOF
condition exists or not. The bit must be cleared and set to one again to force another re-synchronization
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 8: Loss Of Frame (LOF) – When 0, the receive line interface is not in a loss of frame (LOF) condition. When 1,
the receive line interface is in an LOF condition.
Bit 5: Remote Error Indication Count (REIC) – When 0, the remote error indication count is zero. When 1, the
remote error indication count is one or more.
Bit 4: Parity Error Count (PEC) – When 0, the parity error count is zero. When 1, the parity error count is one or
more.
Bit 3: Framing Error Count (FEC) – When 0, the framing error count is zero. When 1, the framing error count is
one or more.
Bit 2: Remote Alarm Indication (RAI) – This bit indicates the current state of the remote alarm indication (RAI),
which is the fifth bit of the G1 byte (G1[5]).
Bit 0: Out Of Frame (OOF) – When 0, the receive frame processor is not in an out of frame (OOF) condition.
When 1, the receive frame processor is in an OOF condition.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Receive Link Status Signal Unstable (LSSU) – When 0, the receive link states signal is stable. When 1,
the receive link states signal is unstable.
15
15
—
—
—
—
7
7
14
14
—
—
—
—
6
6
PLCP.RSR1
PLCP Receive Status Register 1
(1,3,5,7)64h
PLCP.RSR2
PLCP Receive Status Register 2
(1,3,5,7)66h
REIC
13
13
—
—
—
5
5
PEC
12
12
—
—
—
4
4
321
FEC
11
11
—
—
—
3
3
RAI
10
10
—
—
—
2
2
—
—
—
—
9
1
9
1
LSSU
OOF
LOF
—
8
0
8
0