DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 357

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.14.3 Transmit Packet Processor Register Map
The transmit packet processor block uses 10 registers. Note: These registers are shared with the transmit cell
processor registers.
Table 12-50. Transmit Packet Processor Register Map
12.14.3.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 5: Transmit FCS Append Disable (TFAD) – This bit controls whether or not a FCS is appended to the end of
each packet. When 0, the calculated FCS bytes are appended to the end of the packet. When 1, the packet is
transmitted without a FCS.
Bit 4: Transmit FCS-16 Enable (TF16) – When 0, the FCS processing uses a 32-bit FCS. When 1, the FCS
processing uses a 16-bit FCS
Bit 3: Transmit Bit Synchronous Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag
sequence (7Eh). When 1, inter-frame fill is done with all '1's. This bit is ignored in octet aligned mode.
Bit 2: Transmit Scrambling Disable (TSD) – When 0, scrambling is performed. When 1, scrambling is disabled.
Bit 1: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is
from the MSB of the transmit FIFO byte). When 1, bit reordering is enabled (The first bit transmitted is from the LSB
of the transmit FIFO byte).
Bit 0: Transmit Pass-Through Enable (TPTE) – When 0, pass-through mode is disabled and packet processing
is enabled. When 1, the packet processor is in pass-through mode and all packet-processing functions except
scrambling and bit reordering are disabled.
(1,3,5,7)ACh
(1,3,5,7)BCh
(1,3,5,7)AAh
(1,3,5,7)AEh
(1,3,5,7)BAh
(1,3,5,7)BEh
(1,3,5,7)A0h
(1,3,5,7)A2h
(1,3,5,7)A4h
(1,3,5,7)A6h
(1,3,5,7)A8h
(1,3,5,7)B0h
(1,3,5,7)B2h
(1,3,5,7)B4h
(1,3,5,7)B6h
(1,3,5,7)B8h
ADDRESS
15
—
—
0
7
0
REGISTER
PP.TPCR1
PP.TPCR2
PP.TBCR1
PP.TBCR2
PP.TIFGC
PP.TSRIE
PP.TEPC
PP.TSRL
PP.TCR
PP.TSR
—
—
—
—
—
—
14
—
—
0
6
0
Packet Processor Transmit Control Register
Packet Processor Transmit Inter-Frame Gapping Control Register
Packet Processor Transmit Errored Packet Control Register
Reserved
Reserved
Reserved
Reserved
Packet Processor Transmit Status Register
Packet Processor Transmit Status Register Latched
Packet Processor Transmit Status Register Interrupt Enable
Packet Processor Transmit Packet Count Register 1
Packet Processor Transmit Packet Count Register 2
Packet Processor Transmit Byte Count Register 1
Packet Processor Transmit Byte Count Register 2
Unused
Unused
PP.TCR
Packet Processor Transmit Control Register
(1,3,5,7)A0h
TFAD
13
—
0
5
0
REGISTER DESCRIPTION
TF16
12
—
0
0
4
357
Reserved
TIFV
11
0
3
0
Reserved
TSD
10
0
2
0
Reserved
TBRE
9
0
1
0
Reserved
TPTE
8
0
0
0