DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 348

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15 to 0: Receive Header Pattern Comparison Disable (RHPD[15:0]) – Lower 16 bits of 32 bits. Register
description follows next register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Header Pattern Comparison Disable (RHPD[31:16]) - Upper 16 bits of 32 bits.
Receive Header Pattern Comparison Disable (RHPD[31:0]) – These 32 bits indicate whether or not the
associated header bit is checked by the header pattern comparison function. If RHPD[x] is high, the header bit x is
ignored during the header pattern comparison (don't care). If RHPD[x] is low, the associated bit in the header must
match RHP[x] in the receive header pattern control register RHPC.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive LCD Threshold (RLT[15:0]) – These 16 bits indicate the number of consecutive cell periods
the cell delineation state machine must be in an Out of Cell Delineation (OCD) condition before it declares or
terminate a Loss of Cell Delineation (LCD) condition. A value of 0000h causes LCD to be declared at the same
time as OCD. The register has a default value after reset of 360 (decimal).
RHPD15
RHPD31
RHPD23
RHPD7
RLT15
RLT7
15
15
15
0
7
0
0
7
0
0
7
0
RHPD14
RHPD30
RHPD22
RHPD6
RLT14
RLT6
14
14
14
0
6
0
0
6
0
0
6
1
CP.RHPMC1
Cell Processor Receive Header Pattern Mask Control Register 1
(1,3,5,7)C8h
CP.RHPMC2
Cell Processor Receive Header Pattern Mask Control Register 2
(1,3,5,7)CAh
CP.RLTC
Cell Processor Receive LCD Threshold Control Register
(1,3,5,7)CCh
RHPD13
RHPD29
RHPD21
RHPD5
RLT13
RLT5
13
13
13
0
5
0
0
5
0
0
5
1
RHPD28
RHPD20
RHPD12
RHPD4
RLT12
RLT4
12
12
12
0
0
0
0
0
0
4
4
4
348
RHPD11
RHPD27
RHPD19
RHPD3
RLT11
RLT3
11
11
11
0
3
0
0
3
0
0
3
1
RHPD10
RHPD26
RHPD18
RHPD2
RLT10
RLT2
10
10
10
0
2
0
0
2
0
0
2
0
RHPD25
RHPD17
RHPD9
RHPD1
RLT9
RLT1
9
0
1
0
9
0
1
0
9
0
1
0
RHPD24
RHPD16
RHPD8
RHPD0
RLT8
RLT0
8
0
0
0
8
0
0
0
8
1
0
0