DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 73

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 8-21
Figure 8-21. Internal (IFRAC) Transmit Fractional Timing
Figure 8-22
Figure 8-22. Internal (IFRAC) Receive Fractional Timing
8.3.4
The Flexible fractional mode provides the capability to modify the payload data from the cell/packet processor
before inserting it into the DS3 or E3 payload. The bit rate of the payload from the cell/packet processor can be
less than the DS3 or E3 payload bit rate. The interface to the DS3 or E3 payload uses the TSOFIn, TSOFOn,
TDENn, TSERn, RSOFOn, RDENn and RSERn pins. The interface to the cell/packet processor uses the
TPDENIn, TPDENOn, TPDATn, RPDENIn and RPDATn pins. The TPDENIn pin is used to determine the bit rate of
the transmit cell/packet payload data. The TPDENOn pin is high when the data on TPDATn is valid. The delay
between TPDENIn and TPDENOn is three clocks. The RPDENIn pin is used to determine the bit rate of the receive
cell/packet processor data. The cell/packet processor uses the cell/packet data on the RPDATn pin when the
RPDENIn pin is high.
TFOHENO
RFOHENO
TCLKI or
RCLKI or
TCLKO
TGCLK
RCLKO
RGCLK
TFOH
RSER
Flexible Fractional (FFRAC) DS3/E3 Overhead Interface Functinal Timing
shows the timing with the internal fractional transmit port pins.
shows the timing with the internal fractional transmit port pins.
X
X
1
1
X
X
2
2
X
X
FOH
3
3
X
FOH
4
4
FOH
FOH
5
5
FOH
6
6
X
FOH
7
7
X
X
8
8
X
X
9
9
X
X
10
10
X
X
73
11
11
X
X
12
12
X
X
13
13
FOH
X
14
14
FOH
FOH
15
15
FOH
FOH
16
16
X
FOH
17
17
X
X
18
18
X
X
19
19
X
X
20
20
X
X
21
21
X
X
22
22
X
X
23
23
FOH
X
FOH
24
24
FOH