DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 131

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 10-17. E3 PLCP Frame
10.5.11.4 Example E3 G.751 Internal Fractional Mapping
The example E3 G.751 internal fractional mapping shown in Figure 10-16 is accomplished using the internal
fractional block. The first four bits of the E3. G.751 payload is designated fractional overhead This is done by
setting Section A (FRAC.TDASR) register of the fractional block to be overhead and setting its size to be four bits.
The data group size (FRAC.TDGSR) register should be set to the length of the normal payload (1524) or any
number greater than that. The four bits of fractional overhead (E3 frame bits 13,14,15 and 16) can be set to all
ones, all zeros, or a 1010 pattern. Both ATM cell and HDLC packet mapping in this mode is bit aligned. The NAD
bit is ignored.
Figure 10-18. Example E3 G.751 Internal Fractional Frame
10.5.11.5 E3 G.832 Direct Mapping
For mapping into E3 G.832 frames ATM cells are byte aligned or bit aligned, HDLC packets are always bit aligned.
The ATM cell byte/bit alignment is controlled with the NAD bit in the PORT.CR1 register. The NAD bit is ignored
when HDLC packets are mapped into the E3 G.832 frame.
A1
A1
A1
A1
A1
A1
A1
A1
A1
FAS
A2
A2
A2
A2
A2
A2
A2
A2
A2
P8
P7
P6
P5
P4
P3
P2
P1
P0
A N
X X X X
M2
M1
G1
Z3
Z2
Z1
B1
C1
F1
372 Payload Bits
384 Payload Bits
384 Payload Bits
384 Payload Bits
384 bits
Subframe
53 Payload Bytes
53 Payload Bytes
53 Payload Bytes
53 Payload Bytes
53 Payload Bytes
53 Payload Bytes
53 Payload Bytes
53 Payload Bytes
53 Payload Bytes (1 cell)
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