DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 282

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 3: C-bit Parity Error Count (CPEC) – When 0, the C-bit parity error count is zero. When 1, the C-bit parity
error count is one or more. This bit is set to zero in M23 DS3 mode.
Bit 2: Remote Error Indication Count (FBEC) – When 0, the remote error indication count is zero. When 1, the
remote error indication count is one or more. This bit is set to zero in M23 DS3 mode.
Bit 1: P-bit Parity Error Count (PEC) – When 0, the P-bit parity error count is zero. When 1, the P-bit parity error
count is one or more.
Bit 0: Framing Error Count (FEC) – When 0, the framing error count is zero. When 1, the framing error count is
one or more. The type of framing error event counted is determined by T3.RCR.FECC[1:0]
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 11: T3 Framing Format Mismatch Latched (T3FML) – This bit is set when the T3FM bit transitions from zero
to one.
Bit 10: Application Identification Channel Change Latched (AICL) – This bit is set when the AIC bit changes
state.
Bit 9: DS3 Idle Signal Change Latched (IDLEL) – This bit is set when the IDLE bit changes state.
Bit 8: Receive Unframed All 1’s Change Latched (RUA1L) – This bit is set when the RUA1 bit changes state.
Bit 7: Out Of Multiframe Change Latched (OOMFL) – This bit is set when the OOMF bit changes state.
Bit 6: Severely Errored Frame Change Latched (SEFL) – This bit is set when the SEF bit changes state.
Bit 5: Change Of Frame Alignment Latched (COFAL) – This bit is set when the data path frame counters are
updated with a new DS3 frame alignment that is different from the previous DS3 frame alignment.
Bit 4: Loss Of Frame Change Latched (LOFL) – This bit is set when the LOF bit changes state.
Bit 3: Remote Defect Indication Change Latched (RDIL) – This bit is set when the RDI bit changes state.
Bit 2: Alarm Indication Signal Change Latched (AISL) – This bit is set when the AIS bit changes state.
Bit 1: Out Of Frame Change Latched (OOFL) – This bit is set when the OOF bit changes state.
Bit 0: Loss Of Signal Change Latched (LOSL) – This bit is set when the LOS bit changes state.
Reserved
OOMFL
15
15
—
—
7
7
Reserved
SEFL
14
14
—
—
6
6
T3.RSR2
T3 Receive Status Register 2
(1,3,5,7)26h
T3.RSRL1
T3 Receive Status Register Latched 1
(1,3,5,7)28h
Reserved
COFAL
13
13
—
—
5
5
Reserved
LOFL
12
—
12
—
4
4
282
T3FML
CPEC
RAIL
11
11
—
3
3
FBEC
AICL
AISL
10
10
—
2
2
IDLEL
OOFL
PEC
—
9
1
9
1
RUA1L
LOSL
FEC
—
8
0
8
0