DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 174

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
10.10.7 G.751 E3 Framer/Formatter
10.10.7.1 Transmit G.751 E3 Frame Processor
The G.751 E3 frame format is shown in
Figure
10-43. FAS is the Frame Alignment Signal. A is the Alarm indication
bit used to indicate the presence of an alarm to the remote terminal equipment. N is the National use bit reserved
for national use.
Figure 10-43. G.751 E3 Frame Format
FAS
A N
4 Rows
1524 Bit Payload
384 bits
10.10.7.2 Transmit G.751 E3 Frame Generation
G.751 E3 frame generation receives the incoming payload data stream, and overwrites the entire E3 overhead bit
locations.
The first 10 bits of the frame are overwritten with the frame alignment signal (FAS), which has a value of
1111010000b.
The 11th bit of the frame is overwritten with the alarm indication (A) bit. The A bit can be generated automatically,
sourced from the transmit FEAC controller, set to one, or set to zero. The A bit source is programmable (automatic,
FEAC, 1, or 0). If the A bit is generated automatically, it is set to one when one or more of the indicated alarm
conditions is present, and set to zero when all of the indicated alarm conditions are absent. Automatically setting
RDI on LOS, LOF, or AIS is individually programmable (on or off).
The twelfth bit of the frame is overwritten with the national use (N) bit. The N bit can be sourced from the transmit
FEAC controller, sourced from the transmit HDLC overhead controller, set to one, or set to zero. The N bit source
is programmable (FEAC, HDLC, 1, or 0). Note: The FEAC controller will source one bit per frame regardless of
whether the A bit only, the N bit only, or both are programmed to be sourced from the FEAC controller.
Once all of the E3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming E3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off).
10.10.7.3 Transmit G.751 E3 Error Insertion
Error insertion inserts framing errors into the frame alignment signal (FAS). The type of error(s) inserted into the
FAS is programmable (errored FAS bit or errored FAS). An errored FAS bit is a single bit error in the FAS. An
errored FAS is an error in all ten bits of the FAS (a value of 0000101111b is inserted in the FAS). Framing error(s)
can be inserted one error at a time, or in four consecutive frames. The framing error insertion number (single or
four) is programmable.
Single error insertion mode inserts an error at the next opportunity when requested. The multi-error insertion mode
inserts the indicated number of errors at the next opportunities when requested. That is, a single request will cause
multiple errors to be inserted. The requests can be initiated by a register bit (TSEI) or by the manual error insertion
input (TMEI). The error insertion initiation type (register or input) is programmable. The insertion of each particular
error type is individually enabled.
Once all error insertion has been performed, the data stream is passed on to overhead insertion.
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