DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 130
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
DS3184DK
Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3184DK
Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 10-15. DS3 M23 (with C-Bits Used as Payload) Frame
10.5.11.3 E3 G.751 Direct and PLCP Mapping
For direct mapping into E3 G.751 frames, ATM cells and HDLC packets are bit aligned. ATM cells can also be
PLCP mapped to the E3 G.751 frame. When E3 PLCP mapping is used, the first four bits of the payload (E3 frame
bits 13,14,15 and 16) are forced to be 1100 and the rest of the payload is used for the PLCP frame that is
transmitted byte aligned and the NAD bit is ignored.
Figure 10-16. E3 G.751 Frame
In E3 PLCP framing, the ATM cell is always cell aligned into the PLCP frame, HDLC packets cannot be mapped
into PLCP frames. The E3 PLCP frame can only be mapped into a E3 G.751 frame. The NAD control bit is ignored.
M
M
M
X
X
P
P
1
2
1
2
1
2
3
FAS
bits
84
F
F
F
F
F
F
F
A N
11
21
31
41
51
61
71
169
bits
F
F
F
F
F
F
F
384 Payload Bits
376 Payload Bits
384 Payload Bits
384 Payload Bits
12
22
32
42
52
62
72
384 bits
680 Bits
169
bits
130
F
F
F
F
F
F
F
13
23
33
43
53
63
73
169
bits
F
F
F
F
F
F
F
14
24
34
44
54
64
74
bits
84
4 Rows
7 Sub-
Frames
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