DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 332

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 13 to 8: Transmit FIFO Almost Empty Level (TFAE[5:0]) – In POS-PHY packet processing mode, these six
bits indicate the maximum number of four byte groups that can be stored in the Transmit FIFO for it to be
considered "almost empty". E.g., a value of 30 (1Eh) results in the FIFO being "almost empty" when it contains 120
(78h) bytes or less. In cell processing mode, these bits are ignored.
Bits 5 to 0: Transmit FIFO Almost Full Level (TFAF[5:0]) – In POS-PHY packet processing mode, these six bits
indicate the maximum number of four byte groups that can be available in the Transmit FIFO for it to be considered
"almost full". E.g., a value of 30 (1Eh) results in the FIFO being "almost full" when it has 120 (78h) bytes or less
available. In cell processing mode, TFAF[5:2] are ignored, and TFAF[1:0] indicate the maximum number of cells
that can be available in the Transmit FIFO for it to be considered "almost full".
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 4 to 0: Transmit FIFO System Port Address (TPA[4:0]) – These five bits set the Transmit FIFO system
interface port address used to poll the Transmit FIFO for fill status, and select it for data transfer. In Level 2 mode,
if bits TPA[4:0] are set to a value of 1Fh, the port is disabled.
15
15
—
—
—
—
0
7
0
0
7
0
14
14
—
—
—
—
0
6
0
0
6
0
FF.TLCR
FIFO Transmit Level Control Register
(1,3,5,7)82h
FF.TPAC
FIFO Transmit Port Address Control Register
(1,3,5,7)84h
TFAE5
TFAF5
13
13
—
—
0
5
0
0
5
0
TFAE4
TFAF4
TPA4
12
12
—
1
1
0
0
4
4
332
TFAE3
TFAF3
TPA3
11
11
—
0
3
0
0
3
0
TFAE2
TFAF2
TPA2
10
10
—
0
2
0
0
2
0
TFAE1
TFAF1
TPA1
—
9
0
1
0
9
0
1
0
TFAE0
TFAF0
TPA0
—
8
0
0
0
8
0
0
0