DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 269

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Receive FEAC FIFO Data Invalid (RFFI) – When 0, the Receive FIFO data (RFF[5:0]) is valid. When 1, the
Receive FIFO data is invalid (Receive FIFO is empty).
Bits 5 to 0: Receive FEAC FIFO Data (RFF[5:0]) – These six bits are the FEAC code data stored in the Receive
FIFO. RFF[5] is the LSB (last bit received) of the FEAC code (C[6]), and RFF[0] is the MSB (first bit received) of the
FEAC code (C[1]). The Receive FEAC FIFO data (RFF[5:0]) is updated when it is read (lower byte read).
RFFI
15
—
0
7
0
14
—
—
0
6
0
FEAC.RFDR
FEAC Receive FIFO Data Register
(0,2,4,6)DCh
RFF5
13
—
0
5
0
RFF4
12
—
0
0
4
269
RFF3
11
—
0
3
0
RFF2
10
—
0
2
0
RFF1
—
9
0
1
0
RFF0
—
8
0
0
0