DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 138

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
modulus (TMOD[1:0]). It outputs transmit direct packet available (TDXA), transmit polled packet available (TPXA),
and transmit selected packet available (TSPA) signals. The transmit bus is used to transfer packet data whenever
one of the ports is selected for packet data transfer. TSOX is asserted during the first transfer of a packet, TEOP is
asserted during the last transfer of a packet, TERR is asserted when a packet has an error, TMOD indicates the
number of bytes transferred on TDATA during the last transfer of a packet, TSX is asserted when the selected
FIFO's port address has been placed on TDATA, packet data is transferred on TDATA, and the data bus parity is
indicated on TPRTY. All signals are sampled and updated using TSCLK. The TDXA, TPXA, and TSPA signals are
used to indicate when the Transmit FIFO has space available for a programmable number of bytes. There is a
TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has space available
for more than a programmable number of bytes. TDXA goes low when the associated port's Transmit FIFO is full.
TPXA reflects the current status of a port's TDXA signal when the port is polled. TSPA reflects the current status of
a port's TDXA signal when the port is selected. The TPXA and TSPA signals are always driven.
10.6.6.5 POS-PHY Level 2, Receive Side
In POS-PHY Level 2, the Link layer device pulls packets across the system interface. The Link layer device polls
the individual ports to determine which ports have packet data available, and selects a port for packet data transfer.
More than one PHY layer device can be present on a POS-PHY Level 2 bus.
The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[4:0]), and
receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[31:0]), receive parity
(RPRTY), receive start of packet (RSOX), receive end of packet (REOP), receive error (RERR), receive data valid
(RVAL), and receive modulus (RMOD[1:0]), as well as, a receive direct packet available (RDXA) signal and a
receive polled packet available (RPXA) signal. The receive data bus is used to transfer packet data whenever one
of the ports is selected for packet data transfer. RSOX is asserted during the first transfer of a packet, REOP is
asserted during the last transfer of a packet, RERR is asserted when a packet has an error, RMOD indicates the
number of bytes transferred on RDATA during the last transfer of a packet, RVAL is asserted when the receive
data bus is valid, RDATA transfers packet data, and RPRTY indicates the data bus parity. All signals are sampled
and updated using RSCLK. The RDXA and RPXA signals are used to indicate when the Receive FIFO has a
programmable number of bytes or an end of packet available for transfer. There is an RDXA for each port in the
device. RDXA goes high when the associated port's Receive FIFO contains more than a programmable number of
bytes or an end of packet. RDXA goes low when the associated port's Receive FIFO is empty. RPXA reflects the
current status of a port's RDXA signal when the port is polled. The data bus is tri-stated unless REN is asserted
(low) and one of the ports is selected for packet data transfer. The RPXA signal is tri-stated unless one of the ports
is being polled for FIFO fill status.
10.6.6.6 POS-PHY Level 3 (or SPI-3), Receive Side
In POS-PHY Level 3, the DS318x pushes packets across the system interface. The DS318x selects a port for
packet data transfer when it has packet data available. Only one PHY layer device can be present on a POS-PHY
Level 3 (or SPI-3) bus.
The Receive System Interface Bus Controller accepts a receive clock (RSCLK) and receive enable (REN). It
outputs a receive data bus consisting of receive data (RDATA[31:0]), receive parity (RPRTY), receive start of
packet (RSOX), receive end of packet (REOP), receive error (RERR), receive data valid (RVAL), receive start of
transfer (RSX), and receive modulus (RMOD[1:0]). The receive data bus is used to transfer packet data whenever
one of the ports has packet data available for transfer. RSOX is asserted during the first transfer of a packet, REOP
is asserted during the last transfer of a packet, RERR is asserted when a packet has an error, RMOD indicates the
number of bytes transferred on RDATA during the last transfer of a packet, RSX is asserted when the Link layer
port address has been placed on RDATA, RVAL is asserted when the receive data bus is valid, RDATA transfers
packet data, and RPRTY indicates the data bus parity. All signals are sampled and updated using RSCLK. The
data bus is always driven.
In POS-PHY Level 3 (or SPI-3) the Receive System Interface Bus Controller determines which port to transfer data
from using a round-robin arbitration scheme (the ports are checked one after another in numerical order according
to their line number x (R[x]DT[1:8]). A transfer is initiated from a port when it is not almost empty (contains more
data than the almost empty level or contains an end of packet). Transfer from a port is terminated when the
maximum burst length has been transferred, the FIFO is emptied, or an end of packet is transferred while the
Receive FIFO is almost empty (contains the same or less data than the almost empty level and does not contain an
end of packet). When a transfer is terminated, a transfer is initiated from the next available port that is not almost
empty. At the end of a packet or between a transfer from one port and the transfer from the next port, RVAL will go
low for a programmable number of clock cycles (0-7) to allow the POS-PHY master to halt data transfer. At the end
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