DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 370
DS3184DK
Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3184DK
Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Byte Count (RBC[15:0]) – Lower 16 bits of 32 bits. Register description follows next
register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Byte Count (RBC[31:16]) - Upper 16 bits of 32 bits.
Receive Byte Count (RBC[31:0]) – These 32 bits indicate the number of bytes contained in packets stored in the
receive FIFO without an error indication. Note: Bytes discarded due to FCS extraction, system loopback, FIFO
reset, or an overflow condition may be included in this count. This register is updated via the PMU signal (see
Section 10.4.5).
RBC15
RBC31
RBC23
RBC7
15
15
0
7
0
0
7
0
RBC14
RBC30
RBC22
RBC6
14
14
0
6
0
0
6
0
PP.RBCR1
Packet Processor Receive Byte Count Register 1
(1,3,5,7)E8h
PP.RBCR2
Packet Processor Receive Byte Count Register 2
(1,3,5,7)EAh
RBC13
RBC29
RBC21
RBC5
13
13
0
5
0
0
5
0
RBC12
RBC28
RBC20
RBC4
12
12
0
0
0
0
4
4
370
RBC11
RBC27
RBC19
RBC3
11
11
0
3
0
0
3
0
RBC10
RBC26
RBC18
RBC2
10
10
0
2
0
0
2
0
RBC25
RBC17
RBC9
RBC1
9
0
1
0
9
0
1
0
RBC24
RBC16
RBC8
RBC0
8
0
0
0
8
0
0
0
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