DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 347

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bit 1: Receive Bit Reordering Enable (RBRE) – When 0, bit reordering is disabled (The first bit received is stored
in the MSB of the receive FIFO byte). When 1, bit reordering is enabled (The first bit received is stored in the LSB
of the receive FIFO byte).
Bit 0: Receive Pass-Through Enable (RPTE) – When 0, pass-through mode is disabled and cell processing is
enabled. When 1, the cell processor is in pass-through mode, and all cell processing functions except
descrambling and bit reordering are disabled.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Header Pattern (RHP[15:0]) – Lower 16 bits of 32 bits. Register description follows next
register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Header Pattern (RHP[31:16]) - Upper 16 bits of 32 bits.
Receive Header Pattern (RHP[31:0]) – These 32 bits indicate the receive header bit pattern to be detected by the
header pattern comparison function.
RHP15
RHP31
RHP23
RHP7
15
15
0
7
0
0
7
0
RHP14
RHP30
RHP22
RHP6
14
14
0
6
0
0
6
0
CP.RHPC1
Cell Processor Receive Header Pattern Control Register 1
(1,3,5,7)C4h
CP.RHPC2
Cell Processor Receive Header Pattern Control Register 2
(1,3,5,7)C6h
RHP13
RHP29
RHP21
RHP5
13
13
0
5
0
0
5
0
RHP12
RHP28
RHP20
RHP4
12
12
0
0
0
0
4
4
347
RHP11
RHP27
RHP19
RHP3
11
11
0
3
0
0
3
0
RHP10
RHP26
RHP18
RHP2
10
10
0
2
0
0
2
0
RHP25
RHP17
RHP9
RHP1
9
0
1
0
9
0
1
0
RHP24
RHP16
RHP8
RHP0
8
0
0
0
8
0
0
0