DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 135
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DS3184DK
Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3184DK
Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 135 of 400
- Download datasheet (4Mb)
10.6.6 System Interface Bus Controller
The Transmit and Receive System Interface Bus Controller can be programmed to operate as a UTOPIA Level 2,
UTOPIA Level 3, POS-PHY Level 2, or POS-PHY Level 3 (or SPI-3) bus controller. It controls the system interface
bus timing and provides a common interface to the Transmit and Receive FIFO for FIFO status polling and
cell/packet data transfer. Normally, the first byte transmitted is transferred across the system interface as the most
significant byte (TDATA[31:24] in 32-bit mode or TDATA[15:8] in 16-bit mode). If byte reordering is enabled, the
first byte transmitted is transferred across the system interface as the least significant byte (TDATA[7:0]).On the
receive side, the first byte received is transferred across the system interface as the most significant byte
(RDATA[31:24] in 32-bit mode or RDATA[15:8] in 16-bit mode). If byte reordering is enabled, the first byte received
is transferred across the system interface as the least significant byte (RDATA[7:0]).
See
Figure 10-21. Normal Packet Format in 32-Bit Mode
Bit 31
Figure 10-22. Normal Packet Format in 16-Bit Mode
Bit 15
Figure 10-23. Byte Reordered Packet Format in 32-Bit Mode
Bit 31
Byte 4n-7
Byte 4n-3
Byte 2n-3
Byte 2n-1
Byte 4n-4
Byte 4n
Byte 1
Byte 5
Byte 1
Byte 3
Byte 4
Byte 8
Figure
•
•
•
•
•
•
•
•
•
10-21,
Byte 4n-6
Byte 4n-2
Byte 2n-2
Byte 4n-5
Byte 4n-1
Figure
Byte 2n
Byte 2
Byte 6
Byte 2
Byte 4
Byte 3
Byte 7
•
•
•
•
•
•
•
•
•
Bit 0
10-22,
Figure
Byte 4n-5
Byte 4n-1
Byte 4n-6
Byte 4n-2
(n-1)
Byte 3
Byte 7
Byte 2
Byte 6
2
n
1
nd
st
th
•
•
•
•
•
•
10-23, and
th
Transfer
Transfer
Transfer
Transfer
Byte 4n-4
Byte 4n-7
Byte 4n-3
Figure 10-24.
Byte 4n
Byte 4
Byte 8
Byte 1
Byte 5
•
•
•
•
•
•
135
Bit 0
Bit 0
Byte reordering is ignored in 8-bit mode.
(n-1)
(n-1)
2
2
n
n
1
1
nd
nd
st
th
st
th
th
th
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
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