DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1372

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 23 Flash Memory
5. The flash memory is not accessible during programming/erasing operations. Therefore, the
6. After programming/erasing, access to flash memory is inhibited until FKEY is cleared.
7. Switching of the MATs by FMATS is needed for programming/erasing of the user MAT in
8. When the program data storage area indicated by the FMPDR parameter in the programming
Based on these conditions, tables 23.17 and 23.18 show the areas in which the program data can
be stored and executed according to the operation type and mode.
Table 23.17 Executable MAT
Note:
Rev. 3.00 May 17, 2007 Page 1314 of 1582
REJ09B0181-0300
Operation
Programming
Erasing
is not accessible, such as single-chip mode, the required procedure programs, interrupt vector
table, interrupt processing routine, and user branch program should be transferred to on-chip
RAM before programming/erasing of the flash memory starts.
programming/erasing program must be downloaded to on-chip RAM in advance. Areas for
executing each procedure program for initiating programming/erasing, the user program at the
user branch destination for programming/erasing, the interrupt vector table, and the interrupt
processing routine must be located in on-chip memory other than flash memory or the external
address space.
A reset state (RES = 0) for more than at least 100 µs must be taken when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Transitions to the reset state during programming/erasing are inhibited. When the reset signal
is accidentally input to the LSI, a longer period in the reset state than usual (100 µs) is needed
before the reset signal is released.
user boot mode. The program which switches the MATs should be executed from the on-chip
RAM. For details, see section 23.8.1, Switching between User MAT and User Boot MAT.
Please make sure you know which MAT is selected when switching the MATs.
processing is within the flash memory area, an error will occur. Therefore, temporarily transfer
the program data to on-chip RAM to change the address set in FMPDR to an address other
than flash memory.
*
Programming/Erasing is possible to user MATs.
User Program Mode
Table 23.18 (1)
Table 23.18 (2)
Initiated Mode
User Boot Mode*
Table 23.18 (3)
Table 23.18 (4)