DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 906

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
In receiving, the SCIF operates as follows:
1. The SCIF synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
Figure 16.17 shows an example of SCIF receive operation.
Rev. 3.00 May 17, 2007 Page 848 of 1582
REJ09B0181-0300
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed
(overrun error is detected), further reception is prevented.
the SCIF requests a receive-data-full interrupt (RXIF). If the ORER bit is set to 1 and the RIE
bit or REIE bit in SCSCR is also set to 1, the SCIF requests a break interrupt (BRIF).
Synchronization
Serial data
ORER
Figure 16.16 Sample Flowchart for Receiving Serial Data (2)
clock
RDF
Figure 16.17 Example of SCIF Receive Operation
interrupt
request
RXIF
Bit 7
RDF flag cleared
interrupt handler
Data read from
No
Bit 0
LSB
SCFRDR and
to 0 by RXIF
One frame
Clear ORER flag in SCLSR to 0
Overrun error handling
Error handling
interrupt
ORER = 1?
request
RXIF
MSB
Bit 7
End
Yes
Bit 0
Bit 1
BRIF interrupt request
Bit 6
by overrun error
Bit 7