DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 97

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.5
2.5.1
Table 2.10 lists the instructions classified by type.
Table 2.10 Instruction Types
Type
Data transfer
instructions
Arithmetic
operation
instructions
Instruction Set
Instruction Set by Type
Kinds of
Instruction
5
21
Op Code
MOV
MOVA
MOVT
SWAP
XTRCT
ADD
ADDC
ADDV
CMP/cond
DIV1
DIV0S
DIV0U
DMULS
DMULU
DT
EXTS
EXTU
MAC
MUL
Function
Data transfer
Immediate data transfer
Peripheral module data transfer
Structure data transfer
Effective address transfer
T bit transfer
Upper/lower swap
Extraction of middle of linked registers
Binary addition
Binary addition with carry
Binary addition with overflow
Comparison
Division
Signed division initialization
Unsigned division initialization
Signed double-precision multiplication
Unsigned double-precision multiplication
Decrement and test
Sign extension
Zero extension
Multiply-and-accumulate, double-
precision multiply-and-accumulate
Double-precision multiplication
Rev. 3.00 May 17, 2007 Page 39 of 1582
REJ09B0181-0300
Section 2 CPU
Number of
Instructions
39
33