DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 885

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
2
1
0
Bit Name
SCKDT
SPBIO
SPBDT
Initial
value
Undefined R/W
0
Undefined R/W
R/W
R/W
Description
SCK Port Data
Controls the SCK pin in combination with the SCKIO bit
in this register, the C/A bit in SCSMR, and bits CKE1
and CKE0 in SCSCR. Select the SCK pin function in
the PFC (pin function controller) beforehand.
C/A CKE1 CKE0 SCKIO SCKDT: SCK pin state
0
0
0
0
0
0
1
1
1
1
Note: ×: Don't care
Serial Port Break Output Control
Controls the TXD pin in combination with the SPBDT bit
in this register and the TE bit in SCSCR.
Serial Port Break Data
Controls the TXD pin in combination with the SPBIO bit
in this register and the TE bit in SCSCR. Select the
TXD pin function in the PFC (pin function controller)
beforehand.
TE
0
0
0
0
Note: ×: Don't care
Section 16 Serial Communication Interface with FIFO (SCIF)
0
0
0
0
1
1
0
0
1
1
SPBIO SPBDT: TXD pin state
0
1
1
×
0
0
0
1
0
1
0
1
0
1
×:
0:
1:
×:
Rev. 3.00 May 17, 2007 Page 827 of 1582
0
1
1
×
×
×
×
×
×
×
Setting prohibited (initial state)
Low level output
High level output
Transmit data output according
to serial core logic
×:
0:
1:
×:
×:
×:
×:
×:
×:
×:
Setting prohibited
Low level output
High level output
Internal clock output
External clock input to
Setting prohibited
Internal clock output
Internal clock output
External clock input to
Setting prohibited
(initial state)
according to serial core
logic
serial core logic
according to serial core
logic
according to serial core
logic
serial core logic
REJ09B0181-0300