DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 185

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.6
6.6.1
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt from interrupt requests sent,
3. The interrupt controller compares the priority level of the selected interrupt request with the
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR.
8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high
9. The CPU reads the start address of the exception handling routine from the exception vector
according to the priority levels set in interrupt priority registers A to F and H to M (IPRA to
IPRF and IPRH to IPRM). Interrupts that have lower-priority than that of the selected interrupt
are ignored*. If interrupts that have the same priority level or interrupts within a same module
occur simultaneously, the interrupt with the highest priority is selected according to the default
priority shown in table 6.3.
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the
selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If
the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt
controller accepts the request and sends an interrupt request signal to the CPU.
an instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception handling.
level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high
level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception
processing instead of instruction execution as noted in 5. above. However, if the interrupt
controller accepts an interrupt with a higher priority than the interrupt just to be accepted, the
IRQOUT pin holds low level.
table for the accepted interrupt, branches to that address, and starts executing the program.
This branch is not a delayed branch.
Interrupt Operation
Interrupt Sequence
Rev. 3.00 May 17, 2007 Page 127 of 1582
Section 6 Interrupt Controller (INTC)
REJ09B0181-0300