DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1390

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 26 Power-Down Modes
26.3.3
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Rev. 3.00 May 17, 2007 Page 1332 of 1582
REJ09B0181-0300
Bit
3
2 to 0
Bit
7
6
Standby Control Register 3 (STBCR3)
Bit Name
MSTP3

Bit Name
MSTP15
MSTP14
Initial value:
Initial
Value
1
All 0
Initial
Value
1
1
R/W:
Bit:
MSTP
R/W
15
7
1
R/W
R/W
R
R/W
R/W
R/W
MSTP
R/W
14
6
1
Description
Module Stop Bit 3
When this bit is set to 1, the supply of the clock to the
DMAC is halted.
0: DMAC operates
1: Clock supply to the DMAC halted
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Module Stop Bit 15
When this bit is set to 1, the supply of the clock to the
I
0: I
1: Clock supply to I
Module Stop Bit 14
When this bit is set to 1, the supply of the clock to the
SCIF is halted.
0: SCIF operates
1: Clock supply to SCIF halted
MSTP
2
R/W
C2 is halted.
13
5
1
2
C2 operates
MSTP
R/W
12
4
1
MSTP
R/W
11
3
1
MSTP
R/W
10
2
2
1
C2 halted
R
1
1
-
R
0
1
-