DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 682

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.3
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
• Channels 0 to 4
• Channel 5
Where
11.7.4
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 11.121 shows the timing in this case.
Rev. 3.00 May 17, 2007 Page 624 of 1582
REJ09B0181-0300
f =
f =
Caution on Period Setting
Contention between TCNT Write and Clear Operations
f:
MPφ:
N:
Figure 11.121 Contention between TCNT Write and Clear Operations
(N + 1)
MPφ
MPφ
MPφ
MPφ
Address
Address
Write signal
Write signal
Counter clear
Counter clear
signal
signal
TCNT
TCNT
N
Counter frequency
MTU2 peripheral clock operating frequency
TGR set value
TCNT write cycle
TCNT write cycle
N
N
TCNT address
TCNT address
T1
T1
T2
T2
H'0000
H'0000