DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 51

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Table 11.44
CCLR0 to CCLR2 (Channels 1 and 2) ................................................................. 437
TPSC0 to TPSC2 (Channel 0) .............................................................................. 438
TPSC0 to TPSC2 (Channel 1) .............................................................................. 438
TPSC0 to TPSC2 (Channel 2) .............................................................................. 439
TPSC0 to TPSC2 (Channels 3 and 4) ................................................................... 439
TPSC1 and TPSC0 (Channel 5)........................................................................ 440
Setting of Operation Mode by Bits MD0 to MD3 ............................................ 442
TIORH_0 (Channel 0) ...................................................................................... 445
TIORL_0 (Channel 0)....................................................................................... 446
TIOR_1 (Channel 1) ......................................................................................... 447
TIOR_2 (Channel 2) ......................................................................................... 448
TIORH_3 (Channel 3) ...................................................................................... 449
TIORL_3 (Channel 3)....................................................................................... 450
TIORH_4 (Channel 4) ...................................................................................... 451
TIORL_4 (Channel 4)....................................................................................... 452
TIORH_0 (Channel 0) ...................................................................................... 453
TIORL_0 (Channel 0)....................................................................................... 454
TIOR_1 (Channel 1) ......................................................................................... 455
TIOR_2 (Channel 2) ......................................................................................... 456
TIORH_3 (Channel 3) ...................................................................................... 457
TIORL_3 (Channel 3)....................................................................................... 458
TIORH_4 (Channel 4) ...................................................................................... 459
TIORL_4 (Channel 4)....................................................................................... 460
TIORU_5, TIORV_5, and TIORW_5 (Channel 5)........................................... 461
Setting of Transfer Timing by BF1 and BF0 Bits............................................. 483
Output Level Select Function ........................................................................... 496
Output Level Select Function ........................................................................... 497
Setting of Bits BF1 and BF0............................................................................. 499
TIOC4D Output Level Select Function ............................................................ 499
TIOC4B Output Level Select Function............................................................. 500
TIOC4C Output Level Select Function............................................................. 500
TIOC4A Output Level Select Function ............................................................ 500
TIOC3D Output Level Select Function ............................................................ 500
TIOC4B Output Level Select Function............................................................. 501
Output level Select Function............................................................................. 504
Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 ................. 507
Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 ................. 507
Setting of Bits BTE1 and BTE0........................................................................ 510
Register Combinations in Buffer Operation ..................................................... 523
Cascaded Combinations.................................................................................... 527
Rev. 3.00 May 17, 2007 Page li of Iviii