DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 480

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
10.5.4
Do not access the DMAC or DTC registers through DMAC operation. Do not access the DMAC
registers through DTC operation.
10.5.5
When the TXI interrupt in SCI is specified as a DMAC activation source, the TEND flag in the
SCI must not be used as the transfer end flag.
10.5.6
Before modifying the CHCR setting, be sure to clear the DE bit in the respective channel.
10.5.7
Do not use the same on-chip request in multiple channels.
10.5.8
Transfer requests must be input after DMAC settings are completed.
10.5.9
When a conflict occurs between the generation of the NMI interrupt and the DMAC activation, the
NMI interrupt has priority. Thus the NMI bit is set to 1 and the DMAC is not activated.
It takes 1 × Bcyc + 3× Pcyc for determining DMAC stop by NMI, 3 × Bcyc for determining
DMAC activation by DREQ, and 1 × Pcyc for determining DMAC activation by peripheral
modules (Bcyc is the external bus clock cycle, and Pcyc is the peripheral clock cycle).
Rev. 3.00 May 17, 2007 Page 422 of 1582
REJ09B0181-0300
Access to DMAC and DTC Registers through DMAC
Note on SCI as DMAC Activation Source
CHCR Setting
Note on Multiple Channel Activation
Note on Transfer Request Input
Conflict between NMI Interrupt and DMAC Activation